In interline transfer type imaging devices, photogenerated charge is collected on a photo charge collection site or photoreceptor, such as in a photodiode pn junction or under the gate of a photocapacitor, for a period of time and then transferred into a charge coupled register to be detected by an output circuit. In an area array of such photocharge collection sites it is necessary to transfer the collected photocharge, first into a vertical shift register and then to a horizontal shift register, finally, reaching a charge sensitive detector or amplifier. In prior art devices such as disclosed by Oda, U.S. Pat. No. 4,521,797, a vertical shift register is composed of electrode pairs, each of which is formed by a charge storage electrode and a potential barrier electrode, which are arranged so that a charge storage electrode of one pair is connected to a potential barrier electrode of an adjacent pair, to receive the same clock pulse. Such a vertical shift register may then be operated using only two vertical clock sources. FIG. 1 shows, schematically, a plan view of a portion of the light sensing section of such a prior art device. Reference may also be made to FIGS. 2 and 4 of Oda for a more detailed plan view of such a prior art device. Furthermore, in the device disclosed by Oda, a separate transfer gate electrode, which he labels .PHI.s, is clocked to transfer photogenerated charge from the photodiode regions into the CCD shift register. Upon further examination of the device disclosed by Oda it will be realized that the vertical CCD shift register is, in actuality, composed of four conductive elements for each complete stage of the shift register. Referring now to FIG. 1, photodiodes, labeled D.sub.ij, where index number i refers to the ith row and j refers to the jth column in an array of such photodiodes, collect charge generated by incident light. After a period of light exposure the photogenerated charges which have been collected by diodes D.sub.ij are transferred to the corresponding storage regions of the vertical shift register, S.sub.ij, for subsequent shifting to charge detection circuitry. One complete stage of the vertical shift register is then composed of storage region S.sub.ij and barrier region B.sub.ij both controlled by, say, a .PHI..sub.1 clock, and storage region S.sub.1+1,j and barrier region B.sub.1+1,j are controlled by clock .PHI..sub.2. In the device described by Oda, a separately clocked transfer gate electrode transfers charges from each diode, D.sub.ij, to its corresponding storage region S.sub.ij. This transfer operation is indicated by the arrows in FIG. 1. However, again referring to FIG. 1, in the subsequent transferring of the photocharges through the vertical shift register, charge from a given row m-1 must be combined with charge from row m, charge from row m+1 with that from row m+2, etc. This is because one complete stage of the vertical CCD register is composed of a pair of storage regions and their associated barrier regions. This places a limitation on the modes of operation of the device and limits the vertical resolution obtainable in a single charge collection interval.
FIG. 2 shows a more detailed but still schematic cross sectional view of the vertical shift register of the device of FIG. 1, taken along line A--A. Here, semiconductor substrate 70 is provided with a buried channel region 40 and covered with an insulating layer 80. Charge storage electrodes 20 and 50 are formed and additional doping is provided in the regions 65 between electrodes 20 and 50. Additional insulation is formed over electrodes 20 and 50 and overlapping electrodes 30 and 60 are formed. The doping 65 creates barrier regions 25 and 55 in the buried channel and regions 26 and 56 are storage regions. Then, in a manner similar to that described by Oda, clock voltages .PHI..sub.1 and .PHI..sub.2 are connected to the electrode pair 20 and 30 and to the electrode pair 50 and 60, respectively. Thus, the four electrode elements, 20, 30, 50 and 60 comprise one full stage of a two-phase vertical shift register. During charge transfer, any charge that is held in storage region 56 is transferred to storage region 26 when .PHI..sub.2 is at a low voltage and .PHI..sub.1 is at a higher voltage. Any charge accumulated in region 26 is held there by the high .PHI..sub.1 voltage. Thus, if region 56 corresponds to row m-1 of FIG. 1 and if region 26 corresponds to row m, then charges from these two rows are combined when vertical clocking commences and the vertical resolution of the device is diminished. Thus, the vertical resolution of the device is limited by, among other factors, the design tolerances associated with the fabrication of a vertical shift register with four separate conductive elements per shift register stage.
A two-phase vertical shift register device has also been disclosed by Yaushira (Japanese Patent 62-293762) where charges from alternate rows of photodiodes are transferred to the vertical shift register and read out in a first field. Then, the charges from the intervening rows of photodiodes are transferred to the vertical register and read out. This alternate line read-out in two fields is termed an interlaced read out and is suitable for video applications but, as discussed, for example, by Brosiers et al (Technical Digest, IEDM, 1988, pp. 70-73), such a read out is not suitable for electronic still photography. For electronic still photography applications, in order to prevent blur from scene motions, the light produced charges should be read out at a single time, not in two fields. However, for a single field of either of the above-described prior art devices, the vertical resolution is in each case limited by the requirement that the vertical shift register be composed of four separate conductive elements per shift register stage.
Other prior art devices, such as disclosed by Miyatake (European patent application 0148786, Jul. 17, 1985), have utilized a four-phase vertical shift register where alternate rows of photodiodes are read out into the vertical register and then read out in two fields. Again, the vertical resolution in this case is limited by the requirement that the vertical shift register be composed of four separate conductive elements per shift register stage.
Image sensing devices for applications to electronic still photography require all picture elements, or pixels, to be exposed during the same exposure interval. In order to operate an electronic camera without the use of a mechanical shutter it is necessary to simultaneously collect photogenerated charge, say on an array of photodiodes, and then after a suitable exposure interval, transfer the photogenerated charge to a shift register for storage and sequential read out. An interline transfer CCD type device which performs such a function would transfer photocharges from all of an array of photodiodes simultaneously into corresponding vertical shift register storage regions. Then, the photocharges are transferred, line by line, to a horizontal CCD shift register and then to a detector circuit. Clearly, the integrity of the separate photocharges from each diode must be maintained in order to maintain the maximum resolution in the detected image. This integrity is achieved in a device, where each line is read out in sequence, is called a non-interlaced device or a progressive scan device. This mode of operation is not possible with prior art devices such as discussed above. Alternatively, if three levels of overlapping electrodes are employed with a three-phase clocking sequence, such as disclosed by Tsaur et al in IEEE Electron Device Letters, 10, 361-363, 1989, a non-interlaced read-out may be achieved but at the expense of additional process and system complexity and a sacrifice of available photosensitive area.
In U.S. Pat. No. 4,330,796, Anognostopoulos et al disclose a non-interlaced interline transfer type CCD image sensor which employs three electrodes per pixel and a "meander channel" CCD which occupies a large fraction of the total picture element, or pixel, area. However, as discussed in Losee et al, U.S. Pat. No. 4,613,402, if the barrier region implants in the meander channel CCD are not precisely aligned, parasitic potential wells or barriers will be present in the CCD, thus leading to transfer inefficiency and poor performance.